This invention relates to a semiconductor device. More particularly, it relates to technique which will be effective when applied to a package having an LOC (Lead On Chip) structure of a large scale integrated circuit.
To protect a semiconductor chip, it has been customary to mold a semiconductor chip by a resin and to seal it. Various methods have been employed to position leads on a semiconductor chip and to fit them before this sealing is carried out.
When a lead frame equipped with tabs at the center is used, for example, the semiconductor chip is fitted to the tabs before it is sealed. As the prior art technique of this kind, a method which connects electrode pads near and around the semiconductor chip to corresponding inner leads by bonding wires is known.
The common problem with the semiconductor package according to the prior art is that cracks develop along parting lines of molds as the outlet of leads of a metallic lead frame.
Another problem is that an invasion path of contaminant sources in an environment from outside into the semiconductor chip along the metallic leads is relatively short.
Still another problem is that the bonding wires necessary for connecting the inner leads to the electrode pads of the semiconductor chip cannot be crossed mutually.
In a semiconductor device in which a plurality of inner lead portions of leads are bonded onto a circuit formation surface of a semiconductor chip by an adhesive while interposing an electrically insulating tape or film, the inner lead portions and the semiconductor chip are electrically connected by bonding wires and the semiconductor chip is sealed by a mold resin, a semiconductor device having common inner lead portions (bus bar inner leads) in the proximity of the center line of the circuit formation surface of the semiconductor chip in the longitudinal direction has been proposed in order to eliminate the cross-over problem described above (e.g. JP-A-2-246125 laid-open on Oct. 1, 1990).